1. Field of the Invention
The present invention generally relates to semiconductor memories and more particularly, to a circuit configuration of data write and data erase in a nonvolatile semiconductor memory.
2. Description of the Prior Art
FIG. 5 shows a memory cell circuit of a conventional electrically erasable programmable read-only memory (EEPROM). The conventional memory cell circuit includes memory cells 121 to 123 and a peripheral circuit of the memory cells 121 to 123. The peripheral circuit includes a word line 124, a source line 125, a power line 126, bit lines 127 to 129, bit line drivers 130 to 132, data latch circuits 133 to 135, a word line driver 136 and a data line 137. In FIG. 5, each of the memory cells 121 to 123 is constituted by a metal-oxide-semiconductor (MOS) transistor in which a floating gate is formed on a channel connecting a source and a drain and a control gate for controlling potential of the channel is formed on the floating gate.
The word line 124 is connected to the control gates of the memory cells 121 to 123 and potential of the word line 124 is changed by the word line driver 136. The source line 125 is connected to the sources of the memory cells 121 to 123 and a distal end of the source line 125 is grounded. The bit lines 127 to 129 are, respectively, connected to the drains of the memory cells 121 to 123 such that the memory cells 121 to 123 exchange data with the peripheral circuit via the bit lines 127 to 129. By using a high voltage Vpp supplied through the power line 126, the bit line drivers 130 to 132 apply to the bit lines 127 to 129 outputs corresponding to data of the data latch circuits 133 to 135, respectively. The data line 137 is provided for exchanging data with an external device and connects the data latch circuits 133 to 135 to a data input/output port (not shown) for the external device.
In the conventional EEPROM of FIG. 5, when data is written in one of the memory cells 121 to 123, for example, the memory cell 121, the data is initially latched from the data input/output port to all the data latch circuits 133 to 135 by way of the data line 137. Then, potential of the bit line 127 connected to the memory cell 121 for data write is raised by the bit line driver 130 and potential of the word line 124 is raised by the word line driver 136. In the meantime, since potential of the source line 125 is maintained at a ground level, a high voltage is applied between the source and the drain of the memory cell 121 and hot electrons are generated at the channel by the high electric field. The hot electrons are attracted by the high potential of the floating gate of the memory cell 121 so as to be injected into the floating gate of the memory cell 121 and thus, a gate voltage threshold value at which electric current starts flowing between the source and the drain of the memory cell 121 rises. When the gate voltage threshold value has reached a desired value, the potential of the word line 124 and the potential of the bit line 127 connected to the memory cell 121 for data write are lowered and thus, data write is completed.
In the above described data write operation of the conventional EEPROM, since an initial period required for latching the data is far shorter than a latter period required for raising the gate voltage threshold value of the memory cell to the desired value by generating the hot electrons, the data is simultaneously written in as many memory cells as possible by using such a circuit as shown in FIG. 5, so that write time per unit data quantity is reduced, thereby resulting in improvement of its operating efficiency.
However, in the above conventional EEPROM, as the number of the memory cells for simultaneous data write increases, electric current flowing through the memory cells increases immediately after start of data write and a current peak occurs. Therefore, current carrying capacity of the source line 125 and the power line 126 should be designed to be large in conformity with the current peak. Furthermore, in case the high voltage Vpp supplied to the bit lines 127 to 129 is generated internally, boosting capability of a booster should also be designed to be large in conformity with the current peak. As a result, such a problem arises that these design conditions run counter to recent industrial trends towards miniaturization and lower supply voltage.
Thus, in order to lower the current peak necessary for data write, Japanese Patent Laid-Open Publication No. 2001-15716 (2001) proposes a semiconductor memory unit in which a constant-current element for restricting to a predetermined value electric current supplied to the drains of the memory cells is inserted at a spot S between the power source of the high voltage Vpp and the power line 126 in the conventional EEPROM of FIG. 5. However, electric current supplied to the drains of the memory cells varies due to scatter of characteristics of the memory cells, etc. Therefore, in this known semiconductor memory unit, such inconveniences are incurred that in case the predetermined value to which electric current is restricted by the constant-current element is not optimal, the current peak required for data write cannot be lowered and generation efficiency of the hot electrons cannot be increased.
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art, a nonvolatile semiconductor memory in which not only miniaturization and low supply voltage can be obtained through reduction of current carrying capacity and boosting capability by lowering a current peak required for data write but write time can be shortened by raising generation efficiency of hot electrons.
In order to accomplish this object of the present invention, a nonvolatile semiconductor memory which is provided with a plurality of memory elements each having a control gate and a floating gate such that data is stored by electron injection to the floating gate and electron emission from the floating gate, according to the present invention includes an electric current detecting circuit for detecting a drain current supplied to a drain of each of the memory elements. The nonvolatile semiconductor memory further includes a voltage control circuit for controlling a gate voltage supplied to the control gate of each of the memory elements, in accordance with the drain current detected by the electric current detecting circuit.